Style de citation APA (7e éd.)
Sutherland, S. (2017). RTL Modeling with System Verilog for Simulation and Synthesis using System Verilog for ASIC and FPGA design. Tualatin.
Style de citation Chicago (17e éd.)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Sutherland HDL: Tualatin, 2017.
Style de citation MLA (9e éd.)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Tualatin, 2017.
Attention : ces citations peuvent ne pas être correctes à 100%.