APA (7th ed.) Citation
Sutherland, S. (2017). RTL Modeling with System Verilog for Simulation and Synthesis using System Verilog for ASIC and FPGA design. Tualatin.
Chicago Style (17th ed.) Citation
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Sutherland HDL: Tualatin, 2017.
MLA (9th ed.) Citation
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Tualatin, 2017.
Warning: These citations may not always be 100% accurate.