APA-Zitierstil (7. Ausg.)
Sutherland, S. (2017). RTL Modeling with System Verilog for Simulation and Synthesis using System Verilog for ASIC and FPGA design. Tualatin.
Chicago-Zitierstil (17. Ausg.)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Sutherland HDL: Tualatin, 2017.
MLA-Zitierstil (9. Ausg.)
Sutherland, Stuart. RTL Modeling with System Verilog for Simulation and Synthesis Using System Verilog for ASIC and FPGA Design. Tualatin, 2017.
Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.