Ochotnický, S., & Štefanovič, J. (2010). Syntéza VHDL opisu z modelu SIMULINK. STU v Bratislave FIIT.
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Citação norma Chicago
Ochotnický, Stanislav, and Juraj Štefanovič. Syntéza VHDL Opisu Z Modelu SIMULINK. Bratislava: STU v Bratislave FIIT, 2010.
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Citação norma MLA
Ochotnický, Stanislav, and Juraj Štefanovič. Syntéza VHDL Opisu Z Modelu SIMULINK. STU v Bratislave FIIT, 2010.
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Nota: a formatação da citação pode não corresponder 100% ao definido pela respectiva norma.